The functional complexity of integrated circuits has been doubling each year for many years and can be expected to continue increasing at that rate for the forseeable future. The feasibility of larger devices with smaller features is well illustrated by papers in this issue. The motivation to continue this trend is the high cost of interconnecting smaller units and the repeated denonstration that the more complex device soon costs less than the multiple‐chip equivalent. The smaller feature devices also provide faster response and consume less power.
Optical systems: Optical techniques for fabricating devices are generally limited to ≳5 μm linewidths in practical production by the diffraction effects. While contact printing can achieve <2 μm resolutions, the defects caused by contacting the wafer limit the yields, especially when device area is large. Projection printing can give 2‐μm features when small areas are exposed at one time with individual focus correction.
Alternate wavelengths: Electron beams or soft x rays promise the necessary performance in the future because their shorter wavelength avoids significant diffraction limitations.
The ELIPS electron‐image system uses a photocathode coated on an optical master with uv illumination from behind to provide a patterned source of electrons that can be imaged to expose a Si wafer. The parallel exposure of the whole pattern requires but a few seconds. Substrate flatness error may cause significant distortion of the patterns. Techniques have been described for realignment and equipment has been available, but no commercial use of the system has developed.
A step‐and‐repeat electron imaging system has been described in which an electron‐transparent mask is reduced onto the electron‐resist‐coated substrate. Such a system would require time for the stepping, alignment, and exposure of each chip on the substrate, and the electron‐transparent mask would be difficult to fabricate, fragile in construction, and subject to distortions from heating in the electron beam.
Soft x rays may be used for proximity printing of masks having Au features on transparent substrates onto x‐ray‐resist‐coated wafers. One system requires long exposures with 8‐Å radiation through Si substrate masks onto PMMA resists, but achieves good resolution and stability. Another uses 4‐Å radiation with Mylar substrates and Be windows to achieve shorter exposures in air onto special x‐ray resists. Further development will be required before these systems are useful.
While no company can develop all of these systems, it is economically important to each that they have easy access to the most successful technology. Pattern generation: Electrons can be used to generate a pattern as well as to image it onto a wafer. Electrons can be imaged to a point and that point scanned over the resist‐coated substrate and modulated to serially expose the pattern. Such systems are pattern generators in that they expose a hard‐copy pattern from a software description. Many research systems have been constructed using a vector scan of the electron beam to expose each feature in the pattern of a single chip. The substrate is then moved, realigned at the next chip location, and the next pattern written. The aberrations of the electron‐optical system limit the field to a few millimeters for a 1‐μm address size and smaller for the 0.1‐ or 0.2‐μm address commonly used. This limits the device size or requires butting of separate fields which is satisfactory for exploratory work. Settling time is required after long deflection moves with the vector scan, but exposure time is reduced for low‐density patterns. Many exploratory devices have been fabricated by directly exposing resist‐coated substrates using this technique, although the time required for serial exposure is generally too long for economical commercial production.
EBES: An electron‐beam exposure system (EBES) was developed at Bell Laboratories because it is necessary as a pattern generator for use in making masks for various printing methods as well as for direct device exposure. It was designed to provide economical performance at the half‐micron address structure which is important at this time, although it can be modified gracefully to provide higher resolution as required. It has been used to make masks and direct exposures for a year with better performance and at lower cost than alternate optical systems.
The system uses a very small field of electronic deflection combined with a continuously moving servo table. The small (140‐μm) deflection field allows maximum brightness, negligible aberrations, and excellent dimensional control. Laser interferometers measure errors in the table position that are corrected by deflection of the electron beam to compensate for vibrations, distortions, and slow table response. The feedback system provides the deflection speed of electron deflection, the field size of mechanical table motions, and the accuracy of laser interferometers.
A raster scan is used within the 140‐μm‐square field in order to minimize the deflection requirements and ease the problem of data handling so that 10‐MHz data rates can be used. The pattern information from an input tape is decoded and stored in memory so that it can be read out repeatedly for each of the chips in the usual pattern. Only a 128‐μm‐wide stripe of the chip is stored at one time to minimize the memory requirement, and this is written on each chip along a serpentine path on the substrate before the next stripe is decoded and exposed adjacent to the first. The system periodically is used in the electron microscope mode to locate a registration mark to cancel accumulated drift. Realignment of sequential levels in directly exposed devices is accomplished by finding three registration marks and distorting the pattern to exactly fit at these points.
The system will write patterns at a 1 cm2/min rate on Si wafers or chrome mask substrates. A usual 2‐in. (5.08‐cm) wafer will thus require about 20 min, including test patterns. A number of other papers in this issue will describe portions of the system in detail and its application to mask making and direct wafer exposure. A more complete general description is published in the special issue of the IEEE Transactions on Electron Devices on device lithography (July 1975).