Pushing the Envelope

Society's insatiable need for faster, smaller processors to run our everyday electronics is pushing the limits of a key memory component of these devices called Dynamic Random Access Memory (DRAM). To achieve additional functionality and boost the performance of DRAM the enabling technologies must be scaled down while keeping the cost of memory the same. Recently, significant progress in the scalability of DRAM has been made, and now a team of researchers at Imec in Belgium has developed an approach that can push the technology to its ultimate scaling limits.

Until now, progress was based on conventional scaling and modifications to the three main components of the DRAM memory cell: the cell transistor, the cell capacitor and the periphery transistor. The major technical challenge in optimizing performance of the DRAM cell capacitor is reducing the "electrical" thickness of the insulating layer to boost capacitance density and hence the amount of charge (i.e., information) stored in the capacitor while maintaining leakage currents through thicknesses sufficiently large that the stored charge does not deplete. Very high dielectric permittivity insulating films are used to balance these requirements and, to further maximize the capacitor area, manufacturers employ integration schemes with more complicated, 3D shapes that limit further downscaling of the DRAM capacitors, bringing about a third challenge: developing capacitors with maximum specified physical thickness. This constrains all layers of the capacitor, particularly the insulating dielectric, and is in direct conflict with maintaining the leakage currents, the focus of this research.

"The approach taken by our research team stipulated that the ultimate leakage of the MIM capacitor would be determined by the so-called direct tunneling, which depends on several parameters: (1) physical thickness of the dielectric layer, (2) the metal/dielectric barrier, and (3) effective tunneling mass," explains Dr. Ben Kaczer, a member of the research team. "While other optimization efforts focused on the first two parameters, this work focused on the third." Using dielectric film candidate materials titanium oxide (TiO) and strontium titanate (STO) as examples, Dr. Ben Kaczer and his colleagues have demonstrated that the effective tunneling mass is a critical parameter for further DRAM MIM capacitor scaling.

The next step is to find dielectric materials with sufficiently high effective tunneling mass, a parameter not well known in most dielectrics. The Imec research team provides a blueprint to use first-principle calculations for extracting this parameter, which allows quick testing of larger numbers of dielectric materials. A detailed understanding of which particular properties of the dielectric affect the effective tunneling mass will help maximize this parameter by adjusting these properties. Imec is already working with collaborators in industry on follow-on research and development.

These findings will allow researchers to push the technology to its ultimate scaling limits and develop next-generation DRAM-type memories, which in turn will translate into more powerful daily-life applications requiring huge amounts of processing memory. Dr. Kaczer concludes, "Increased capacity can make possible memory-hungry applications such as natural control of digital appliances and smartphones, including voice and gesture, augmented reality, searching and indexing, high-definition entertainment and video communication.”