Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Hu, Chan-Yuan; Chen, Jone F.; Chen, Shih-Chih; Chang, Shoou-Jinn; Wang, Shih-Ming; Lee, Chih-Ping; Lee, Kay-Ming

doi:doi:10.1116/1.3359612

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Journal of Vacuum Science & Technology B / Volume 28 / Issue 2 / Regular Articles

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J. Vac. Sci. Technol. B 28, 391 (2010); http://dx.doi.org/10.1116/1.3359612 (7 pages)

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Chan-Yuan Hu¹, Jone F. Chen¹, Shih-Chih Chen², Shoou-Jinn Chang¹, Shih-Ming Wang¹, Chih-Ping Lee³, and Kay-Ming Lee³

¹Department of Electrical Engineering and Institute of Microelectronics Center for Micro/Nano Science and Technology, Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 70101, Taiwan
²Department of Electrical Engineering, National Yunlin University of Science and Technology, Touliu 640, Taiwan
³United Microelectronics Corporation, Tainan Science-Based Industrial Park, Tainan 74145, Taiwan

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(Published online 26 March 2010)

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Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and V_{cc_min} can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

Article Outline

INTRODUCTION
EXPERIMENT
RESULTS AND DISCUSSION
CONCLUSION

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KEYWORDS and PACS

Keywords

CMOS integrated circuits, compressive strength, isolation technology, leakage currents, low-power electronics, MOSFET, SRAM chips, STI, BTBT, mismatch, Boron, Vcc_min, SRAM

PACS

85.40.-e

Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology
85.30.Tv

Field effect devices

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History

Received 16 June 2009
Accepted 16 February 2010
Published online 26 March 2010

Digital Object Identifier

http://dx.doi.org/10.1116/1.3359612

PUBLICATION DATA

ISSN

1071-1023 (print)

1520-8567 (online)

Publisher

American Vacuum Society

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